In a synchronous operation (e.g., between computer systems or between input/output means in digital telephone exchanges,) a timing accuracy of better than plus/minus 0.5% or is required, where the clock pulse frequency in the transmission of data may vary from 64 kHz to 1200 Hz. Particularly with high clock pulse frequencies, there is a problem when data is received by a computer for processing and distribution, this being to keep a constant data output flow within given accuracy limits for a continuous data input flow.
It is known to use a buffer store, where outgoing data are stored for transmission at a rate dependent on the space occupied in the buffer store. It is also known, with D/A signal conversion, to control a voltage-controlled oscillator depending on the degree of occupation in the buffer store, and subsequently to achieve frequency variations within the permitted plus or minus 0.5% via controllable division of the oscillator frequency. The method, however, requires a complicated circuit structure.